1. Field of the Invention
The present invention relates to a pulse write driver circuit in which current consumption is minimized in a writing operation and data bus lines are precharged upon completion of the writing operation.
2. Description of the Prior Art
FIG. 1 is a circuit diagram of a conventional pulse write driver circuit and FIG. 2 is a timing diagram of signals in the pulse write driver circuit in FIG. 1. Data input transfer positive and negative signals D and /D are applied to NAND gates G1 and G2. In intervals T0-T1 and T5-T6 other than write intervals T1-T5, output signals DI and /DI from the NAND gates G1 and G2 are precharged with logical "1" regardless of the data input transfer positive and negative signals D and/D because a write enable signal WE is logically "0". At the moment T1 that a writing operation is started, the write enable signal WE becomes logical "1" and the output signals DI and /DI from the NAND gates G1 and G2 have their inverted states according to states of the data input transfer positive and negative signals D and /D through the NAND gates G1 and G2. Namely, because both the output signals DI and /DI from the NAND gates G1 and G2 were precharged with logical "1" before the time T1, one (for example, DI) thereof remains at logical "1", whereas the other (for example, /DI) goes from logical "1" to logical "0".
Subsequently, inverters 121-123 and a NOR gate G4 constituting a pulse generator are operated. In the interval (pulse width) T1-T2, a node N2 becomes logical "1" and a node N3 then becomes logical "1" through a NOR gate G5 and an inverter I3. As a result, NMOS transistors MN1 and MN2 are turned, thereby causing the output signals DI and /DI from the NAND gates G1 and G2 to be transferred to positive and negative data bus lines DB and /DB, respectively.
In the case where the states of the data input transfer positive and negative signals D and /D are changed in the write intervals (for example, T3), one (for example, DI) of the output signals DI and /DI from the NAND gates G1 and G2 goes from logical "1" to logical "0" and the other (for example, /DI) goes from logical "0" to logical "1". Subsequently, inverters I11-I13 and a NOR gate G3 constituting a pulse generator are operated. In the interval T3-T4, a node N1 becomes logical "1" and the node N3 then becomes logical "1" through the NOR gate G5 and the inverter 13. As a result, the NMOS transistors MN1 and MN2 are turned, thereby causing the output signals DI and /DI from the NAND gates G1 and G2 to be transferred to the positive and negative data bus lines DB and /DB, respectively.
As mentioned above, in the conventional pulse write driver circuit, the writing operation is performed only in the intervals T1-T2 and T3-T4 necessary to the writing operation and it is not performed in the remaining intervals T2-T3 and T4-T5. Therefore, current consumption can be minimized and a direct current (DC) current path can be blocked in the writing operation.
However, the conventional pulse write driver circuit has a disadvantage in that it is turned off upon completion of the writing operation, resulting in an increase in the time required in charging the data bus lines of a ground voltage with a power source voltage to perform the subsequent writing operation.